FPGAs provide a reconfigurable solution for implementing DSP applications, higher DSP throughput, and more raw data processing power than DSP processors. The DSP processor’s fixed hardware architecture is not suitable for some applications that require customized DSP function implementations. Therefore, fixed hardware architecture such as bus performance bottlenecks, a fixed number of multiply accumulate (MAC) blocks, fixed memory, fixed hardware accelerator blocks, and fixed data widths limit DSP processors. Although these DSP processors are programmable through software, their hardware architecture is not flexible. Specialized DSP processors can implement many of these applications. This chapter introduces DSP Builder for implementing digital signal processing (DSP) designs on AlteraFPGAs.ĭSP Systems in FPGAs The DSP market includes the following rapidly evolving applications, which cover a broad spectrum of performance and cost requirements: ■ 3–4Īdditional Information Document Revision History. 3–1 Obtaining and Installing DSP Builder. Installing DSP Builder System Requirements. Introducing DSP Builder Advanced and Standard Blocksets.
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1–5 Software with Hardware Acceleration Flow. 1–1 Software Design Flow with DSP Processors. Introducing DSP Design DSP Systems in FPGAs. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.Ĭhapter 1. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Patent and Trademark Office and in other countries. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. DSP Builder Handbook Volume 1: Introduction to DSP Builderġ01 Innovation Drive San Jose, CA 95134 HB_DSPB_INTRO-4.0ĭocument last updated for Altera Complete Design Suite version: Document publication date:
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